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+ / + yjgp vkokpi ku etkvkecn yjgp vkokpi ku etkvkecn sm530 approved product low emi spectrum spread clock international microcircuits,inc. 1/5/99 525 los coches st., milpitas, 95035 408-263-6300, fax 408-263-6571 rev. 1.6 http:/www.imicorp.com page 1 of 16 features reduces systemic emi. modulates external source clock. 3 - 5 volt power supply. 14 to 120 mhz.operating frequency range output is multiplied or divided by 1, 2 or 4. digitally controlled modulation. ttl/cmos compatible outputs. center and down spread modulation. compliant with all major cisc, risc and dsp processors. low short term jitter. synchronous output enable. power down mode for low current operation available in 20 pin ssop and tssop packages. applications desktop/laptop computer modems scanners, printers, copiers, fax machines, mfps disk and cd-rom drives automotive and embeddedsystems networking, lan/wan digital cameras, games lcd displays benefits time to market lower cost of compliance programmable emi reduction no degradation in rise/fall times lower component and pcb layer count general description the imi sm530 is a spectrum spread clock modulator designed for the purpose of reducing the electro- magnetic interference (emi) found in todays high speed digital systems. the sm530 is well suited for a wide range of digital system applications that require a reduction of radiated energy. this unwanted radiated energy is usually found in the odd harmonics of digital system clocks. by increasing the bandwidth of the digital clock, measured emi at the fundamental and harmonic frequencies is greatly reduced. this reduction in radiated energy can significantly reduce the cost of complying with regulatory requirements and time to market, without degrading clock and timing signals. the imi sm530 is extremely versatile and flexible in that program control is available for each of the operating modes. program control is provided for input frequency, output frequency multiplication, output bandwidth, center/down spread of fout, modulation on/off and fout state during power down mode depending on the range of operation, the output clock, fout, can be a multiple (1, 2, 4) or a fraction (1, 1/2, 1/4) of the input frequency. the sm530 can synchronously stop the modulated output at the low logic level. the power- down mode adds the flexibility of operating in a completely static mode for reduced standby current and simplified system board testing. there are many benefits to using the sm530 low emi clock modulator. the most important benefit is reducing the amount of clock related emi by as much as 12 - 18 db., depending on the application. refer to sm532 datasheet for the 16 pin soic version, which only supports center-spread operation.
+ / + yjgp vkokpi ku etkvkecn yjgp vkokpi ku etkvkecn sm530 approved product low emi spectrum spread clock international microcircuits,inc. 1/5/99 525 los coches st., milpitas, 95035 408-263-6300, fax 408-263-6571 rev. 1.6 http:/www.imicorp.com page 2 of 16 figure 1. block diagram ordering information part no. package operating temperature range imiSM530AYB 20 pin ssop 0 0 c to 70 0 c imism530atb 20 pin tssop 0 0 c to 70 0 c marking example: imi SM530AYB date code, lot# imiSM530AYB flow b = commercial package y = ssop t = tssop revisions imi device number oscin oscout sscg and power down control divide by r phase detector vco divide by n divide by 1, 2, 4 r0 r1 s0 s1 fout refou t s2 s3 d_c stop lf sson 10 5 4 14 11 17 16 1 2 7 20 15 69
+ / + yjgp vkokpi ku etkvkecn yjgp vkokpi ku etkvkecn sm530 approved product low emi spectrum spread clock international microcircuits,inc. 1/5/99 525 los coches st., milpitas, 95035 408-263-6300, fax 408-263-6571 rev. 1.6 http:/www.imicorp.com page 3 of 16 figure 2. sm530, ssop/tssop package pin assignment pin descriptions pin no. pin name i/o type description 1,2 oscin, oscout i/o cmos pins form an on-chip reference oscillator when connected to terminals of an external parallel resonant crystal. oscin may be connected to a ttl/cmos external clock source. ac coupling may be required. if oscin is connected to an external clock other than crystal, leave oscout (pin 2) unconnected. the input frequency range is 14 to 120 mhz @ 5.0 vdc 3 avdd power power analog circuit positive power supply. 4 d_c i ttl input selection pin used to determine the center frequency position of modulated fout (pin 15). pin 4 has internal pull-down resistor. d_c = 0: down spread. d_c = 1: center spread. 5 stop i ttl when = 1, synchronously stops fout clock at a logic low state. pin 5 has internal pull-down resistor. 6,9 s0, s1 i ttl input control used to select the frequency multiplication at fout, relative to the reference clock. see table on page 5. s0 has internal pull-down, s1 has internal pull-up. 7 lf o analog single ended tri-state output of the phase detector. a two pole passive loop filter is connected to lf. see table on page 7 for proper values. 8 avss ground ground analog circuit ground. 10 sson i ttl input control pin used to enable modulation at the fout pin. sson = 0 = modulation on, sson = 1 = modulation off. has internal pull-down. 11, 14 s3, s2 i ttl input control pins, set the amount of modulation at fout. see table on page 6 for settings. s2 has internal pull-up, s3 has internal pull-down. 12 dvdd power power digital positive power supply. should be kept separate from analog power for best performance. 13 dvss ground ground digital circuit ground. 15 fout o ttl modulated clock output. 16, 17 r1, r0 i ttl input pins control the input frequency range as described in table on page 5. r0 and r1 have internal pull-up. 18 ovss ground ground oscillator circuit ground. can be common to dvss. 19 ovdd power power oscillator circuit positive power supply. can be common to dvdd. 20 refout o ttl buffered output of the crystal or external clock input. (unmodulated) table 1. 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 oscin oscout avdd d_c stop s0 lf avss s1 sson refout. ovdd ovss r0 r1 fout s2 dvss s3 dvdd
+ / + yjgp vkokpi ku etkvkecn yjgp vkokpi ku etkvkecn sm530 approved product low emi spectrum spread clock international microcircuits,inc. 1/5/99 525 los coches st., milpitas, 95035 408-263-6300, fax 408-263-6571 rev. 1.6 http:/www.imicorp.com page 4 of 16 absolute maximum ratings this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, precautions should be taken to avoid application of any voltage higher than the absolute maximum rated voltages to this circuit. for proper operation, vin and vout should be constrained to the range, vss < ( vin or vout) < vdd. all digital inputs are tied high or low internally. refers to electrical specifications for operating supply range. item symbol min. max. units supply voltage vdd 0 6.0 vdc input, relative to vss virvss -0.3 vdd +0.3 vdc output, relative to vss vorvss -0.3 vdd +0.3 vdc avdd relative to dvdd d vpp -100 +100 mv avss relative to dvss d vss -100 +100 mv temperature, operating top 0 + 70 0 c temperature, storage tst - 65 + 150 0 c table 2. electrical characteristics characteristic symbol min. typ. max. units input low voltage vil - - 0.8 vdc input high voltage vih 2.0 - - vdc input low current iil - - 100 m a input high current iih - - 100 m a output low voltage iol= 8ma, vdd = 5v vol - - 0.4 vdc output high voltage ioh = 8ma, vdd = 5v voh vdd-1.0 - - vdc output low voltage iol= 5ma, vdd = 3.3v vol - - 0.4 vdc output high voltage ioh = 3ma,vdd = 3.3v voh 2.4 - - vdc input capacitance (pin-1) c in1 -3-pf output capacitance (pin-2) c in2 -5-pf pull-up resistor values (pins 9, 14, 16 and 17) rpu 100k 167k 300k ohms pull-down resistor values (pins 4, 5, 6, 10, 11) rpd 150k 250k 350k ohms tri-state leakage current (pins 7, 15 and 20) ioz - 5.0 - m a static supply current (power down mode) idd - - 250 m a 5 volt dynamic supply current (operating mode) icc - 25 30 ma 3 volt dynamic supply current (operating mode) icc - 18 20 ma short circuit current (fout) isc - - 30 ma test measurements performed at vdd = 3.3v +/-5% and 5v +/-10%, ta = 0 c to 70 c table 3.
+ / + yjgp vkokpi ku etkvkecn yjgp vkokpi ku etkvkecn sm530 approved product low emi spectrum spread clock international microcircuits,inc. 1/5/99 525 los coches st., milpitas, 95035 408-263-6300, fax 408-263-6571 rev. 1.6 http:/www.imicorp.com page 5 of 16 timing characteristics characteristic symbol min typ max units output rise time measured at 10% - 90% @ 5 vdc ttlh 3.3 3.5 3.8 ns output fall time measured at 10% - 90% @ 5 vdc tthl 2.1 2.3 2.5 ns output rise time measured at 0.8v - 2.0v @ 5 vdc ttlh 0.7 0.75 0.8 ns output fall time measured at 0.8v - 2.0 v @ 5 vdc tthl 0.6 0.7 0.8 ns output rise time measured at 10% - 90% @ 3.3 vdc ttlh 4.8 5.0 5.4 ns output fall time measured at 10% - 90% @ 3.3 vdc tthl 2.9 3.2 3.4 ns output rise time measured at 0.8v - 2.0v @ 3.3 vdc ttlh 1.6 1.75 1.9 ns output fall time measured at 0.8v - 2.0 v @ 3.3 vdc tthl 1.1 1.3 1.5 ns output duty cycle tsymf1 45 50 55 % peak-to peak jitter one sigma (sson = 1) tj1s - 250 500 ps measurements performed at vdd = 3.3v +/-5% and 5v +/-10%, ta = 0 c to 70 c, cl = 15pf, fout = 50.0 mhz. table 4. frequency selection table the following table provides the necessary information for setting the control lines for proper operation of the sm530 and for any frequency within its operating range. note that the table includes operating frequencies at 3.3 and 5.0 vdc. the 3.3 vdc columns are lower in frequency than the 5.0 vdc operation due to the characteristics of the vco. vdd = 5 volts +/- 10% vdd = 3.3 volts +/- 5% fin (range) (mhz) fout/ fin fout (range) (mhz) multiplier settings input range settings fin (range) (mhz) fout/ fin fout (range) (mhz) min max x min max s1 s0 r1 r0 min max x min max see note 0 0 x x see note 14 30 1 14 30 0 1 0 1 14 22.5 1 14 22.5 14 30 2 28 60 1 0 0 1 14 22.5 2 28 45 14 30 4 56 120 1 1 0 1 14 22.5 4 56 90 30 60 0.5 15 30 0 1 1 0 25 45 0.5 12.5 22.5 30 60 1 30 60 1 0 1 0 25 45 1 25 45 30 60 2 60 120 1 1 1 0 25 45 2 50 90 60 120 0.25 15 30 0 1 1 1 50 90 0.25 12.5 22.5 60 120 0.5 30 60 1 0 1 1 50 90 0.5 25 45 60 120 1 60 120 1 1 1 1 50 90 1 50 90 note: selects power down state, see table 7 below. x = dont care condition. table 5. frequency selection table
+ / + yjgp vkokpi ku etkvkecn yjgp vkokpi ku etkvkecn sm530 approved product low emi spectrum spread clock international microcircuits,inc. 1/5/99 525 los coches st., milpitas, 95035 408-263-6300, fax 408-263-6571 rev. 1.6 http:/www.imicorp.com page 6 of 16 modulation and power down selections the bandwidth of the modulation applied to fout is controlled by two input control lines, s2 and s3. also, s2 and s3 control the state the sm530 will go to when the power down mode is selected. the power down mode is selected when both s0 and s1 are set to a logic state 0. refer to the tables below for the proper selection of modulation bandwidth and power down state. modulation selection table modulation settings\ d_c = 0 down spread d_c = 1 center spread total bandwidth s3 s2 low high low high 1.25 % 0 0 98.75 % 100 % 99.375 % 100.625 % 2.50 % 0 1 97.50 % 100 % 98.75 % 101.25 % 5.00 % 1 0 95.00 % 100 % 97.50 % 102.50 % 10.0 % 1 1 90.00 % 100 % 95.00 % 105.00 % table 6. modulation selection table power down selection table fout state s0 s1 s2 s3 factory test 0 0 0 1 hi-z 0011 00000 10010 table 7. power down selection table note: the stop and power down functions are two separate operations. selecting stop does not place the sm530 in the power down mode. power down is selected by setting s0 = 0 and s1 = 0.
+ / + yjgp vkokpi ku etkvkecn yjgp vkokpi ku etkvkecn sm530 approved product low emi spectrum spread clock international microcircuits,inc. 1/5/99 525 los coches st., milpitas, 95035 408-263-6300, fax 408-263-6571 rev. 1.6 http:/www.imicorp.com page 7 of 16 loop filters the sm530 requires an external loop filter to provide the proper operation and modulation profile for a given input frequency. the loop filter is connected to pin 7 (lf) of the sm530 and is a typical 2 pole low pass filter. since the sm530 operates over such a wide range of frequencies, the loop filter will change depending on the frequency of operation. the following loop filter values are recommended for best performance and modulation profile at 3.0 volts and 5.0 volts vdd. operating voltage is measured at the vdd pin of the sm530. notice that the selection of loop filter values only depends on the input frequency and vdd voltage, and does not depend on the r and s settings. figure 3. recommended loop filter recommended loop filter values input range vdd +/-5% input frequency range (mhz) r1 (k w ) c6 (pf) c7 (pf) loop filter # low 3.3 14.0 to 22.5 1.0 10,000 1,000 1 middle 3.3 25.0 to 45.0 1.0 10,000 1,000 1 high 3.3 50.0 to 90.0 1.0 10,000 1,000 1 input range vdd +/-10% input frequency range (mhz) r1 (k w ) c6 (pf) c7 (pf) loop filter # low 5.0 14.0 to 19.9 1.0 10 , 000 1 , 000 1 low 5.0 20.0 to 24.9 1.5 6,800 680 2 low 5.0 25.0 to 29.9 2.0 3,900 390 3 middle 5.0 30.0 to 39.9 1.0 10,000 1,000 1 middle 5.0 40.0 to 49.9 1.5 6,800 680 2 middle 5.0 50.0 to 59.9 2.0 3,900 390 3 high 5.0 60.0 to 79.9 1.0 10,000 1,000 1 high 5.0 80.0 to 99.9 1.5 6,800 680 2 high 5.0 100.0 to 120.0 2.0 3,900 390 3 table 8. the component values listed in table 8 are recommended values using commonly manufactured components. note that there are actually 3 different sets of loop filter values. due to the vco characteristics, the table is divided in to 3 volt operation and 5 volt operation. referring to the table above, it is apparent that one set of loop filter values is all that is needed in the 3 volt operation. in the 5 volt operation, each input operating range is divided into 3 sections which require a different loop filter for optimal performance. the best loop filter for any application is the one that, provides the required emi reduction, maintains system integrity, has a modulation profile shown on page 8 and uses commonly available components. lf lf #1 lf lf #2 lf lf #3 c6 10,000 p f c7 1,000 p f r1 1 k ohm c6 6,800 p f c7 680 p f r1 1.5 k ohm c6 3,900 p f c7 390 p f r1 2 k ohm
+ / + yjgp vkokpi ku etkvkecn yjgp vkokpi ku etkvkecn sm530 approved product low emi spectrum spread clock international microcircuits,inc. 1/5/99 525 los coches st., milpitas, 95035 408-263-6300, fax 408-263-6571 rev. 1.6 http:/www.imicorp.com page 8 of 16 sscg modulation profile the modulation rate of the sm530 within any range is typically 20 - 40 khz. with the correct loop filter connected to pin 7, the following profile will provide the best emi reduction. this profile can be seen on a time domain analyzer. figure 4. modulation profile theory of operation the sm530 is a phase lock loop (pll) type clock generator using direct digital synthesis (dds). by precisely controlling the bandwidth of the output clock, the sm530 becomes a low emi clock generator. the theory and detailed operation of the sm530 will be discussed in the following sections. emi all digital clocks generate unwanted energy in their harmonics. conventional digital clocks are square waves with a duty cycle that is very close to 50 %. because of the 50/50 duty cycle, digital clocks generate most of their harmonic energy in the odd harmonics, i.e.; 3 rd , 5 th , 7 th etc. it is possible to reduce the amount of energy contained in the fundamental and harmonics by increasing the bandwidth of the fundamental clock frequency. conventional digital clocks have a very high q factor, which means that all of the energy at that frequency is concentrated in a very narrow bandwidth, consequently, higher energy peaks. regulatory agencies test electronic equipment by the amount of peak energy radiated from the equipment. by reducing the peak energy at the fundamental and harmonic frequencies, the equipment under test is able to satisfy agency requirements for electro-magnetic interference (emi). conventional methods of reducing emi have been to use shielding, filtering, multi-layer pcbs etc. the sm530 uses the approach of reducing the peak energy in the clock by increasing the clock bandwidth, and lowering the q. 50.000 50.156 50.312 50.468 50.625 49.844 49.687 49.531 time (microseconds) fout freq. (mhz) +1.25% 2.5% -1.25% 0 5 10 15 20 25 30 35 fmax fcenter fmin 49.375
+ / + yjgp vkokpi ku etkvkecn yjgp vkokpi ku etkvkecn sm530 approved product low emi spectrum spread clock international microcircuits,inc. 1/5/99 525 los coches st., milpitas, 95035 408-263-6300, fax 408-263-6571 rev. 1.6 http:/www.imicorp.com page 9 of 16 sscg sscg uses a patented technology of modulating the clock over a very narrow bandwidth and controlled rate of change, both peak and cycle to cycle. the sm530 takes a narrow band digital reference clock in the range of 14 - 120 mhz and produces a clock that sweeps between a controlled start and stop frequency and precise rate of change. the bandwidth of the output clock is programmable. using two control lines on the sm530, the bandwidth of the modulated clock can be controlled over four descrete settings, 1.25, 2.50, 5.0 and 10%. to understand what happens to an sscg clock, consider that we have a 50 mhz clock with a 50 % duty cycle. from a 50 mhz clock we know the following; clock frequency = fc = 50 mhz. clock period = tc = 1/50 mhz = 20 ns. figure 5. unmodulated clock consider that this 50 mhz clock is applied to the oscin input of the sm530, either as an externally driven clock or as the result of a parallel resonant crystal connected to pins 1 and 2 of the sm530. also consider that the sm530 is programmed for the following operation; range (r0, r1) = 0, 1 mid range multiplier (s0, s1) = 0, 1 x1 d_c = 1 center spread sson = 1 modulation is off % modulation (s2, s3) = 1, 0 2.50 % spread tc = 20 ns. 50 % 50 %
+ / + yjgp vkokpi ku etkvkecn yjgp vkokpi ku etkvkecn sm530 approved product low emi spectrum spread clock international microcircuits,inc. 1/5/99 525 los coches st., milpitas, 95035 408-263-6300, fax 408-263-6571 rev. 1.6 http:/www.imicorp.com page 10 of 16 from the above parameters, the output clock at fout will be 50.625 mhz. with modulation turned off, the frequency of fout will always rest at the high end of the programmed spectrum. in this case, +1.25 % of 50 mhz is .625 mhz, equals 50.625 mhz. when modulation is turned on, the clock at fout begins sweeping downward to the minimum extreme of -1.25 % of 50 mhz which is 50 mhz - .625 mhz = 49.375 mhz. when the clock reaches 49.375, the sm530 begins sweeping back up to the maximum extreme of 50.625 mhz. if we were to look at this clock on a spectrum analyzer we would see the following picture. keep in mind that this is a drawing of a perfect clock with no noise. we see that the original 50 mhz reference clock is at the center frequency, cf, and the minimum and maximum extremes are positioned symmetrically about the center frequency. this type of modulation is called center- spread . diagram 6 illustrates this as it is seen on a spectrum analyzer. note that when modulation is turned off, the fout clock is at the maximum extreme of the bandwidth. figure 6. diagram 7 below shows our 50 mhz clock as it would be seen on an oscilloscope. the top trace is the non- modulated reference clock, or the refout clock at pin 20. the bottom trace is the modulated clock at pin 15. from this comparison chart you can see that the frequency is decreasing and the period of each successive clock is increasing. the tc measurements on the left and right of the bottom trace indicate the period of the clock as it moves from the center frequency at 50 mhz and the minimum frequency at 49.375 mhz. extremes of the clock. intermediate clock changes are small and accumulate to achieve the total period deviation. the reverse of this diagram would show the clock period gettting smaller as the frequency increases. figure 7. period comparison chart there are certain cases where center spread modulation is not applicable. if the maximum design frequency of the intended application is 50 mhz and becomes unstable above 50 mhz, then increasing the clock to 50.625 mhz might cause unwanted system problems. to accommodate this situation, the sm530 has an operating mode where the maximum fout frequency never exceeds the reference frequency, not including any multiplier that might be applied. this type of modulation is called down spread . the effective center frequency of the fout clock is shifted down by one-half the amount of the applied modulation. 49.375 mhz min. 50.00mhz center 50.625 m h max. modulatio n off. tc = 20.253 ns. tc = 20.00 ns.
+ / + yjgp vkokpi ku etkvkecn yjgp vkokpi ku etkvkecn sm530 approved product low emi spectrum spread clock international microcircuits,inc. 1/5/99 525 los coches st., milpitas, 95035 408-263-6300, fax 408-263-6571 rev. 1.6 http:/www.imicorp.com page 11 of 16 if the amount of clock spread is set for 2.50%, the effective center frequency of fout is now 1.25 % less than 50 mhz or 49.375 mhz, when modulation is turned on. when modulation is turned off, the fout frequency will go to 50.0 mhz, since this is the maximum extreme of the applied modulation settings. the one drawback to down spread modulation is that the effective center frequency of the clock is, in this case, 1.25 % slower, which means that the performance of the system may be 1.25 % slower. using the above operating parameters for the sm530 and selecting down spread, the operating bandwidth will be as follows; range (r0, r1) = 0, 1 mid range multiplier (s0, s1) = 0, 1 x1 d_c = 0 down spread sson = 0 modulation is on % modulation (s2, s3) = 1, 0 2.50 % spread to calculate the frequency extremes for these conditions in down spread mode, first determine the effective center frequency, cf. in this case cf is; cf = oscin - (oscin x % spread) cf = 50 mhz - (50 mhz x .0125) cf = 50 mhz - 0.625 mhz cf = 49.375 mhz with the effective center frequency at 49.375 mhz, we can now determine the minimum and maximum extremes. fmax = cf + (cf x % spread) fmin = cf - (cf x % spread) fmax = 49.375 + (49.375 x .0125) fmin = 49.375 - (49.375 x .0125) fmax = 49.375 + .617 fmin = 49.375 - .617 fmax = 49.99 mhz fmin = 48.758 mhz another way of calculating the bandwidth in the down spread mode is to use the oscin frequency as the starting point and multiplying the % spread by 2. this assumes that the multiplier is 1. if the multiplier is 2, then you would use 2 times the oscin in the formula. fmax = oscin fmin = oscin - (oscin x (2 x % spread)) fmin = 50 mhz - (50 x (2 x .0125)) fmin = 50 - 1.25 fmin = 48.75 mhz
+ / + yjgp vkokpi ku etkvkecn yjgp vkokpi ku etkvkecn sm530 approved product low emi spectrum spread clock international microcircuits,inc. 1/5/99 525 los coches st., milpitas, 95035 408-263-6300, fax 408-263-6571 rev. 1.6 http:/www.imicorp.com page 12 of 16 this is illustrated in the diagram to the right. you can see that the effective center frequency is 49.375 mhz and the min and max extremes are 1.25 % on either side of the center. or using the second approach, the oscin frequency is the max frequency and the min frequency is 2.5 % down from the reference. looking at diagram 8, you will note that the peak amplitude of the 50 mhz non-modulated clock is higher than the wideband modulated clock. this difference in peak amplitudes between modulated and unmodulated clocks is the reason why sscg clocks are so effective in digital systems. this and the previous illustrations refer to the fundamental frequency of a clock. a very important characteristic of the sscg clock is that the bandwidth of the harmonics is multiplied by the harmonic number. in other words, if the bandwidth of a 50 mhz clock is 1.35 mhz, the bandwidth of the 3 rd harmonic will be 3 times 1.35, or 4.05 mhz. the amount of bandwidth is relative to the amount of peak energy in the clock. consequently, the wider the bandwidth, the greater the energy reduction of the clock. figure 8. most applications will not have a problem meeting agency specifications at the fundamental frequency. it is the higher harmonics that usually cause the most problems. with an sscg clock, the bandwidth and peak energy reduction increases with the harmonic number. consider that the 11 th harmonic of our 50 mhz clock is 550 mhz. with a total spread of 1.35 mhz at 50 mhz, the spread at the 11 th harmonic would be 14.85 mhz which greatly reduces the peak energy content. it is typical to see as much as 12 to 18 db. of reduction at the higher harmonics, due to a modulated clock. referring to diagram 6 on page 10 and diagram 8 above, you can see that the peak amplitude of the non- modulated clock is much higher than the peak amplitude of the modulated clock. this is the reason the sm530 is used for emi reduction. the amount of emi reduction is dependent on the application. the difference in the peak energy of the modulated clock and the non-modulated clock in typical applications will see a 2 - 3 db. reduction at the fundamental and as much as 8 - 10 db. reduction at the intermediate harmonics, 3 rd , 5 th , 7 th etc. at the higher harmonics, it is quite possible to reduce the peak harmonic energy, compared to the unmodulated clock, by as much as 12 to 18 db. the db reduction for a give frequency and spread can be calculated using a simple formula. this formula is only helpful in determining a relative db reduction for a given application. this formula assumes an ideal clock with 50% duty cycle and therfore only predicts the emi reduction of even harmonics. other circumstances such as non-ideal clock and noise will affect the actual db reduction. the formula is as follows; db = 6.5 + 9(log10(f)) + 9(log10(p)) where; f = frequency in mhz, p = total % spread (2.5% = .025) using a 50 mhz clock with a 2.5% spread, the theoretical db reduction would be; db @ 50 mhz (fund) = 6.5 + 15.29 - 14.42 = 7.37 db @ 150 mhz (3rd) = 6.5 + 19.58 - 14.42 = 11.66 db @ 550 mhz (11th) = 6.5 + 24.66 - 14.42 = 16.74 48.75 mhz min 49.375 mhz center 50.00 mhz max
+ / + yjgp vkokpi ku etkvkecn yjgp vkokpi ku etkvkecn sm530 approved product low emi spectrum spread clock international microcircuits,inc. 1/5/99 525 los coches st., milpitas, 95035 408-263-6300, fax 408-263-6571 rev. 1.6 http:/www.imicorp.com page 13 of 16 modulation profile the sm530 moves from max. to min. frequencies of its bandwidth at a pre-determined rate and profile. the modulation frequency is determined by the input frequency and an internal divider. all 3 operating ranges modulate the fout clock at from 20 to 40 khz. the three operating ranges are 14 - 30 mhz, 30 - 60 mhz and 60 to 120 mhz. if oscin = 15 mhz, the modulation rate is 20 khz. if oscin is 60 mhz, in mid-range, the modulation rate would be 40 khz. to provide the proper modulation rate the input reference frequency is divided by a fixed number in each range. the input reference frequency is divided by 750 in low range, 1500 in mid range and 3000 in the high range. from these numbers, the modulation rate can be determined for any input frequency. example: oscin = 45.378 mhz, input range = mid, input divisor = 1500 fmod = oscin /1500 fmod = 30.252 khz if you have a clock frequency that was on the boundary of the mid-range and the high range of operation, the choice of selecting which range to use would be determined by which modulation rate is desired. if you choose the mid-range, the modulation rate would be 40 khz, while choosing the high range would yield a 20 khz modulation rate. there is some operational overlap between ranges, such that 58 mhz in the mid-range would give the same results as 58 mhz in the high-range, except for the modulation rate. this type of operation is not recommended unless it is thoroughly tested. the modulation profile of the sm530 is not a linear sweep from max to min and back. the oscin reference clock determines the modulation frequency but the internal sscg control logic determines the actual modulation profile. the modulation profile can best be described by comparing the instantaneous frequency at fout with time. the illustration in diagram 9 below is a representation of the modulation profile of the sm530 as displayed on a time domain analyzer. figure 9. frequency profile in time domain 50.000 50.156 50.312 50.468 50.625 49.844 49.687 49.531 time (microseconds) fout freq. (mhz) +1.25% 2.5% -1.25% 0 5 10 15 20 25 30 35 fmax fcenter fmin 49.375
+ / + yjgp vkokpi ku etkvkecn yjgp vkokpi ku etkvkecn sm530 approved product low emi spectrum spread clock international microcircuits,inc. 1/5/99 525 los coches st., milpitas, 95035 408-263-6300, fax 408-263-6571 rev. 1.6 http:/www.imicorp.com page 14 of 16 as can be seen from the diagram above, the fout/time profile progresses through frequencies depending on where it is in the sweep. if the frequency is in the middle of the sweep, the rate of change is slower compared to the rate at the extremes of the band. when the frequency is nearing the end of the band, it is moving through these frequencies faster, since it has to sweep through these same frequencies again after reversing direction. this modulation profile is one of the key elements to the sm530. using a linear sweep through all frequencies would not give as good of results in emi reduction. application notes and schematics the schematic diagram shown below is a simple minimum component application example of an sm530 design. in the case shown below, the control lines are configured for the following parameters; input frequency: mid-range multiplier: x1 modulation: 2.50 % sson: on refer to loop filter values on table 8, page 7, for operation at 3.3 volts dc. * l1 and c9 are required when y1 is a 3rd. overtone crystal. figure 10. application schematic vcc = 3.3 vdc modulated clock output reference clock output (not modulated) * * vdd vdd c5 27 pf. y1 50 mhz c8 27 pf. c1 22 uf. c2 0.1 uf. c4 0.1 uf. r2 10 ohm. c3 0.1 uf. sm530 oscin 1 oscout 2 dvdd 12 dvss 13 avss 8 avdd 3 ovdd 19 ovss 18 fout 15 refout 20 r0 17 r1 16 s0 6 s1 9 s2 14 s3 11 d_c 4 lf 7 sson 10 stop 5 c7 1000 pf. c6 10,000 pf. r1 1 k l1 330 nh. c9 .033 uf.
+ / + yjgp vkokpi ku etkvkecn yjgp vkokpi ku etkvkecn sm530 approved product low emi spectrum spread clock international microcircuits,inc. 1/5/99 525 los coches st., milpitas, 95035 408-263-6300, fax 408-263-6571 rev. 1.6 http:/www.imicorp.com page 15 of 16 the sm530 has an internal analog power and ground and a digital power and ground. in the example above, the digital and analog circuits are connected together. if noise is a concern, it is recommended that the analog and digital power and grounds be separated. the loop filter shown above is recommended for operation at 3.14 - 3.47 vdc. this filter can also be used in 5.0 vdc operations when operating in the low frequency end of each of the three input frequency ranges. refer to table 8 on page 7 for loop filter information. also note, the crystal, y1, is a third overtone 50 mhz crystal, which requires an inductor and decoupling capacitor to oscout. diagram 11 below shows the equivalent internal oscillator circuit for the sm530. figure 11. equivalent oscillator circuit. pcb layout example the sm530 spectrum spread clock is a pll type hybrid circuit. this means that is contains both digital and analog circuits on the same die. the phase detector, loop filter and vco are analog circuits that must operate in a very low noise environment for best performance. there are several ways to keep this noise to a minimum, such as bypass capacitors on all power pins and separating the analog and digital power and ground planes. the diagram below uses the first approach of placing bypass capacitors as close to every power pin as possible. in addition, all ground pins should be connected directly to the ground plane with little or no trace length. note also that only the power and ground circuits of the sm530 have been shown. other circuits such as the loop filter components must be located as close to the loop filter pin as possible, for best performance. figure 12. sm530 single power plane pcb layout 1 2 xin xout e q uivalent oscillator circuit . . 1 2 250 k 3 pf 5 pf vss 0.1 uf. 22 uf. vcc vss 10 ohm 0.1 uf. 0.1 uf. vss vss pin 1 vss vss
+ / + yjgp vkokpi ku etkvkecn yjgp vkokpi ku etkvkecn sm530 approved product low emi spectrum spread clock international microcircuits,inc. 1/5/99 525 los coches st., milpitas, 95035 408-263-6300, fax 408-263-6571 rev. 1.6 http:/www.imicorp.com page 16 of 16 package dimensions and drawings 20 pin ssop outline dimensions inches millimeters symbol min nom max min nom max a 0.068 0.073 0.078 1.73 1.86 1.99 a 1 0.002 0.005 0.008 0.05 0.13 0.21 a 2 0.066 0.068 0.070 1.68 1.73 1.78 b 0.010 0.012 0.015 0.25 0.30 0.38 c 0.005 0.006 0.009 0.13 0.15 0.22 d 0.278 0.284 0.289 7.07 7.20 7.33 e 0.205 0.209 0.212 5.20 5.30 5.38 e 0.0256 bsc 0.65 bsc h 0.301 0.307 0.311 7.65 7.80 7.90 a 0 4 8 0 4 8 l 0.022 0.030 0.037 0.55 0.75 0.95 20 pin tssop outline dimensions inches millimeters symbol min nom max min nom max a - - .047 - - 1.20 a 1 .002 .004 .006 0.05 0.10 0.15 a 2 - - .035 - - 0.90 b .007 0.95 .012 0.19 .245 0.30 c------ d .252 .256 .260 6.40 6.50 6.60 e .169 .173 .177 4.30 4.40 4.50 e .026 bsc 0.65 bsc h .246 .252 .258 6.25 6.40 6.55 a0 0 4 0 8 0 0 0 4 0 8 0 l .020 .025 .030 0.50 0.62 5 0.75 disclaimer international microcircuits, inc, reserves the right to change or modify the information contained in this data sheet, without notice. international microcircuits, inc., does not assume any liability arising out of the application or use of any product or circui t described herein. international microcircuits, inc., does not convey any license under its patent rights nor the rights of others. international microcircuits, inc. does not authorize its products for use as critical components in life-support systems or critical medical instruments, where a malfunction or failure may reasonably be expected to result in significant injury to the user. e a a 1 a 2 e h a l c d e a a 1 a 2 e h a l c d b b

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